Systolic Registers; Double Accumulation Register; Output Register Bank; Operational Mode Descriptions - Altera Cyclone V Device Handbook

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Systolic Registers

Accumulation

Systolic Registers

There are two systolic registers per variable precision DSP block. If the variable precision DSP block is not

configured in systolic FIR mode, both systolic registers are bypassed.

The first set of systolic registers consists of 18-bit and 19-bit registers that are used to register the 18-bit and

19-bit inputs of the upper multiplier, respectively.

The second set of systolic registers are used to delay the chainout output to the next variable precision DSP

You must clock all the systolic registers with the same clock source as the output register bank.

The double accumulation register is an extra register in the feedback path of the accumulator. Enabling the

double accumulation register will cause an extra clock cycle delay in the feedback path of the accumulator.

This register has the same

By enabling this register, you can have two accumulator channels using the same number of variable precision

The positive edge of the clock signal triggers the 64-bit bypassable output register bank and is cleared after

The following variable precision DSP block signals control the output register per variable precision DSP

This section describes how you can configure an Cyclone V variable precision DSP block to efficiently

support the following operational modes:

Independent Multiplier Mode

Altera Corporation

Adds the current

result to the previous

accumulate result.

This function takes

the current result,

converts it into two's

complement, and adds

it to the previous

settings as the output register bank.

Variable Precision DSP Blocks in Cyclone V Devices

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