Altera Cyclone V Device Handbook page 543

5-12
Lightweight HPS-to-FPGA Bridge Master Signals
Signal
1 bit
WVALID
1 bit
WREADY
Table 5-18: Lightweight HPS-to-FPGA Bridge Master Write Response Channel Signals
Signal
12 bits
BID
2 bits
BRESP
1 bit
BVALID
1 bit
BREADY
Table 5-19: Lightweight HPS-to-FPGA Bridge Master Read Address Channel Signals
Signal
12 bits
ARID
21 bits
ARADDR
4 bits
ARLEN
3 bits
ARSIZE
2 bits
ARBURST
2 bits
ARLOCK
4 bits
ARCACHE
3 bits
ARPROT
1 bit
ARVALID
1 bit
ARREADY
Table 5-20: Lightweight HPS-to-FPGA Bridge Master Read Data Channel Signals
Signal
12 bits
RID
32 bits
RDATA
2 bits
RRESP
Altera Corporation
Width Direction
Output
Input
Width Direction
Input
Input
Input
Output
Width Direction
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Width Direction
Input
Input
Input
Description
Write data channel valid
Write data channel ready
Description
Write response ID
Write response
Write response channel valid
Write response channel ready
Description
Read address ID
Read address
Burst length
Burst size
Burst type
Lock type Valid values are 00 (normal access) and
01 (exclusive access)
Cache policy type
Protection type
Read address channel valid
Read address channel ready
Description
Read ID
Read data
Read response
cv_54005
2013.12.30
HPS-FPGA AXI Bridges
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