Altera Cyclone V Device Handbook page 316

CV-53001
2013.05.06
Registered Mode
To eliminate the FIFO latency uncertainty for applications with stringent datapath latency uncertainty
requirements, bypass the FIFO functionality in registered mode to incur only one clock cycle of datapath
latency when interfacing the transmitter channel to the FPGA fabric. Configure the FIFO to registered mode
when interfacing the transmitter channel to the FPGA fabric or PCIe hard IP block to reduce datapath
latency. In registered mode, the low-speed parallel clock that is used in the transmitter PCS clocks the FIFO.
Phase Compensation Mode
The transmitter phase compensation FIFO compensates for any phase difference between the read and write
clocks for the transmitter control and data signals. The low-speed parallel clock feeds the read clock, while
the FPGA fabric interface clock feeds the write clock. The clocks must have 0 ppm difference in frequency
or a FIFO underrun or overflow condition may result.
The FIFO supports various clocking modes on the read and write clocks depending on the transceiver
configuration.
Related Information
Transceiver Clocking in Cyclone V Devices
Byte Serializer
The byte serializer divides the input datapath by two to run the transceiver channel at higher data rates while
keeping the FPGA fabric interface frequency within the maximum limit.
The byte serializer supports operation in single- and double-width modes. The datapath clock rate at the
output of the byte serializer is twice the FPGA fabric transmitter interface clock frequency. The byte serializer
forwards the least significant word first followed by the most significant word.
Note: You must use the byte serializer in configurations that exceed the maximum frequency limit of the
FPGA fabric transceiver interface.
Byte Serializer in Single-Width Mode
The byte serializer forwards the LSByte first, followed by the MSByte. The input data width to the byte
serializer depends on the channel width option. For example, in single-width mode with a channel width of
20 bits, the byte serializer sends out the least significant word tx_parallel_data[9:0] of the parallel
data from the FPGA fabric, followed by tx_parallel_data[19:10].
Table 1-12: Input and Output Data Width of the Byte Serializer in Single-Width Mode for Cyclone V Devices
Mode
Single-width
Transceiver Architecture in Cyclone V Devices
Send Feedback
Input Data Width to the
Byte Serializer
16
20
Output Data Width from the
Byte Serializer
8
10
Registered Mode
Byte Serializer Output Ordering
Least significant 8 bits of the 16-
bit output first
Least significant 10 bits of the
20-bit output first
Altera Corporation
1-29