Altera Cyclone V Device Handbook page 746

11-68
Alternative Boot Operation for eMMC Card Devices
• Set up the descriptors as described in Internal DMA Controller Transmission Sequences and Internal
DMA Controller Reception Sequences.
• Set the use internal DMAC bit (use_internal_dmac) of the ctrl register to 1.
4. Set the card device frequency to 400 kHz using the clkdiv registers. For more information, refer to
Clock Setup. Ensure that the card clock is running.
5. Wait for a time that ensures that at least 74 card clock cycles have occurred on the card interface.
6. Set the data_timeout field of the tmout register equal to the card device total access time, N
7. Set the blksiz register to 0x200 (512 bytes).
8. Set the bytcnt register to multiples of 128K bytes, as indicated by the BOOT_SIZE_MULT value in
the card device.
9. Set the rx_wmark field in the fifoth register. Typically, the threshold value can be set to 512, which
is half the FIFO buffer depth.
10. Set the cmdarg register to 0xFFFFFFFA.
11. Initiate the command, by setting the cmd register with the following fields:
• start_cmd = 1
• enable_boot = 1
• expect_boot_ack:
• If a start-acknowledge pattern is expected from the card device, set expect_boot_ack to 1.
• If a start-acknowledge pattern is not expected from the card device, set expect_boot_ack to
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0.
• card_number = 0
• data_expected = 1
• cmd_index = 0
• Set the remainder of cmd register bits to 0.
12. If no start-acknowledge pattern is expected from the card device (expect_boot_ack set to 0) jump
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to step 15.
13. Wait for the Command Done interrupt.
14. This step handles the case where a start-acknowledge pattern is expected (expect_boot_ack was set
to 1 in step
a. If the Boot ACK Received interrupt is not received from the controller within 50 ms of initiating the
command
process and start with normal discovery.
If internal DMA controller mode is used for the boot process, the controller performs the following
steps after the Boot ACK Received timeout:
• The DMA descriptor is closed.
• The ces bit in the idsts register is set to 1, indicating the Boot ACK Received timeout.
• The ri bit of the idsts register is not set.
b. If the Boot ACK Received interrupt is received, the software driver must clear this interrupt by writing
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1 to it.
Within 0.95 seconds of the Boot ACK Received interrupt, the Boot Data Start interrupt must be
received from the controller. If this does not occur, the software driver must discontinue the boot
process and start with normal discovery.
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11).
(step 11), the start pattern was not received. The software driver must discontinue the boot
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cv_54011
2013.12.30
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