Altera Cyclone V Device Handbook page 193

Hide thumbs Also See for Cyclone V:

Table of Contents

I/O banks between two DLLs have the flexibility to create multiple frequencies and multiple-type interfaces.

These banks can use settings from either or both adjacent DLLs. For example,

settings from

The reference clock for each DLL may come from the PLL output clocks or clock input pins.

If you have a dedicated PLL that only generates the DLL input reference clock, set the PLL mode to

Direct Compensation to achieve better performance (or the Quartus II software automatically

changes it). Because the PLL does not use any other outputs, it does not have to compensate for any

clock paths.

DLL Reference Clock Input for Cyclone V Devices

Table 6-11: DLL Reference Clock Input from PLLs for Cyclone V E (A2, A4, A5, A7, and A9), GX (C4, C5, C7, and

C9), and GT (D5, D7, and D9) Devices—Preliminary

Table 6-12: DLL Reference Clock Input from PLLs for Cyclone V GX (C3) Device—Preliminary

Table 6-13: DLL Reference Clock Input from PLLs for Cyclone V SE A2, A4, A5, and A6 Devices, Cyclone V SX

C2, C4, C5, and C6 Devices, and Cyclone V ST D5 and D6 Devices—Preliminary

External Memory Interfaces in Cyclone V Devices

Send Feedback

, while DQS2R can get its phase-shift settings from

DLL Reference Clock Input for Cyclone V Devices

can get its phase-shift

Bottom Right

Bottom Right

Bottom Right

Altera Corporation

Chapters

Table of Contents