Altera Cyclone V Device Handbook page 783

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2013.12.30
USB 2.0 OTG Controller
Registers in the system manager control the HPROT field of the USB master port of the USB 2.0 OTG
Controller.
Note: Register bits should be accessed only when the master interface is guaranteed to be in an inactive
state.
Related Information
USB 2.0 OTG Controller
SD/MMC Controller
Registers in the system manager control the HPROT field of the SD/MMC master port.
Note: Register bits should be accessed only when the master interface is guaranteed to be in an inactive
state.
The system manager allows software to select the clock's phase shift for cclk_in_drv and
cclk_in_sample by setting the drive clock phase shift select (drvsel) and sample clock phase shift
select (smplsel) bits of the sdmmc register.
Related Information
SD/MMC Controller
Watchdog Timer
The system manager controls the watchdog timer behavior when the CPUs are in debug mode. The system
manager sends a pause signal to the watchdog timers depending on the setting of the debug mode bits of
the L4 watchdog debug register (wddbg). Each watchdog timer built into the MPU subsystem is automatically
paused when its associated CPU enters debug mode.
Related Information
Watchdog Timer
Boot ROM Code
Registers in the system manager control whether the boot ROM code configures the pin multiplexing for
boot pins after a warm reset. Set the warm-reset-configure-pin-multiplex for boot pins bit (warmrstcfg-
pinmux) of the boot ROM code register to enable or disable this control.
Note: The boot ROM code always configures the pin multiplexing for boot pins after a cold reset.
Registers in the system manager also control whether the boot ROM code configures the I/O pins used
during the boot process after a warm reset. Set the warm reset configure I/Os for boot pins bit
(warmrstcfgio) of the ctrl register to enable or disable this control. By default, the boot ROM code always
configures the I/O pins used by boot after a cold reset.
When CPU1 is released from reset and the boot ROM code is located at the CPU1 reset exception address
(for a typical case), the boot ROM reset handler code reads the address stored in the CPU1 start address
register (cpu1startaddr) and passes control to software at that address.
System Manager
Send Feedback
on page 18-1
on page 11-1
on page 24-1
USB 2.0 OTG Controller
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