Altera Cyclone V Device Handbook page 875

17-26
Example: Buffer Read
frame. The software driver should discard the dummy bytes based on the start address of the buffer and size
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of the frame.
Example: Buffer Read
If the transmit buffer address is 0x00000FF2 (for 32-bit data bus), and 15 bytes need to be transferred, then
the DMA reads five full words from address 0x00000FF0, but when transferring data to the MTL transmit
FIFO buffer, the extra bytes (the first two bytes) are dropped or ignored. Similarly, the last 3 bytes of the last
transfer are also ignored. The DMA always ensures it transfers a full 32-bit data to the MTL transmit FIFO
buffer, unless it is the end-of-frame.
Example: Buffer Write
If the receive buffer address is 0x0000FF2 (for 64-bit data bus) and 16 bytes of a received frame need to be
transferred, then the DMA writes 3 full words from address 0x00000FF0. But the first 2 bytes of first transfer
and the last 6 bytes of the third transfer have dummy data.
Buffer Size Calculations
The DMA does not update the size fields in the transmit and receive descriptors. The DMA updates only
the status fields (RDES and TDES) of the descriptors. The driver has to perform the size calculations. †
The transmit DMA transfers the exact number of bytes (indicated by buffer size field of TDES1) towards
the MAC. If a descriptor is marked as first (FS bit of TDES1 is set), then the DMA marks the first transfer
from the buffer as the start of frame. If a descriptor is marked as last (LS bit of TDES1), then the DMA marks
the last transfer from that data buffer as the end-of frame to the MTL. †
The receive DMA transfers data to a buffer until the buffer is full or the end-of frame is received from the
MTL. If a descriptor is not marked as last (LS bit of RDES0), then the descriptor's corresponding buffer(s)
are full and the amount of valid data in a buffer is accurately indicated by its buffer size field minus the data
buffer pointer offset when the FS bit of that descriptor is set. The offset is zero when the data buffer pointer
is aligned to the data bus width. If a descriptor is marked as last, then the buffer may not be full (as indicated
by the buffer size in RDES1). To compute the amount of valid data in this final buffer, the driver must read
the frame length (FL bits of RDES0[29:16]) and subtract the sum of the buffer sizes of the preceding buffers
in this frame. The receive DMA always transfers the start of next frame with a new descriptor. †
Note: Even when the start address of a receive buffer is not aligned to the data width of system bus, the
system should allocate a receive buffer of a size aligned to the system bus width. For example, if the
system allocates a 1,024-byte (1 KB) receive buffer starting from address 0x1000, the software can
program the buffer start address in the receive descriptor to have a 0x1002 offset. The receive DMA
writes the frame to this buffer with dummy data in the first two locations (0x1000 and 0x1001). The
actual frame is written from location 0x1002. Thus, the actual useful space in this buffer is 1,022
bytes, even though the buffer size is programmed as 1,024 bytes, because of the start address offset. †
Transmission
Transmission functions use transmit descriptors.
Related Information
Transmit Descriptor
TX DMA Operation: Default (Non-OSF) Mode
The transmit DMA engine in default mode proceeds as follows:
1. The Host sets up the transmit descriptor (TDES0-TDES3) and sets the Own bit (TDES0[31]) after setting
up the corresponding data buffer(s) with Ethernet frame data.
Altera Corporation
on page 17-37
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†
Ethernet Media Access Controller
cv_54017
2013.12.30
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