Active Serial Configuration; Data Clock (Dclk) - Altera Cyclone V Device Handbook

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Active Serial Configuration

Figure 7-4: Multiple Device FPP Configuration Using an External Host When Both Devices Receive the Same
Data
Connect the resistor to a supply that
provides an acceptable input signal for the
FPGA device. V
enough to meet the V IH specification of
the I/O on the device and the external
host. Altera recommends powering up all
configuration system I/Os with V
Memory
ADDR DATA[7..0]
External Host
(MAX II Device,
MAX V Device, or
Microprocessor)
The pins of the device in the chain are connected to GND, allowing configuration for these devices to
nCE
begin and end at the same time.
Active Serial Configuration
The AS configuration scheme supports AS x1 (1-bit data width) and AS x4 (4-bit data width) modes. The
AS x4 mode provides four times faster configuration time than the AS x1 mode. In the AS configuration
scheme, the Cyclone V device controls the configuration interface.
Related Information
Cyclone V Device Datasheet
Provides more information about the AS configuration timing.

DATA Clock (DCLK)

Cyclone V devices generate the serial clock,
configuration scheme, Cyclone V devices drive control signals on the falling edge of
configuration data on the following falling edge of this clock pin.
The maximum
multi-device configuration scheme. You can source
the internal oscillator, you can choose a 12.5, 25, 50, or 100 MHz clock under the Device and Pin Options
dialog box, in the Configuration page of the Quartus II software.
After power-up,
the clock source and frequency to use by reading the option bit in the programming file.
Altera Corporation
must be high
CCPGM
.
CCPGM
V V
CCPGM CCPGM
FPGA Device Master
10 kΩ 10 kΩ
CONF_DONE
nSTATUS
nCE
GND
DATA[]
nCONFIG
DCLK
Buffers
Connect the repeater buffers between the
FPGA master and slave device for DATA[]
and DCLK for every fourth device.
frequency supported by the AS configuration scheme is 100 MHz except for the AS
DCLK
is driven by a 12.5 MHz internal oscillator by default. The Cyclone V device determines
DCLK
Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices
MSEL[4..0]
nCEO N.C.
GND
, that provides timing to the serial interface. In the AS
DCLK
using
DCLK CLKUSR
For more information, refer to
the MSEL pin settings.
FPGA Device Slave
MSEL[4..0]
CONF_DONE
nSTATUS
nCEO N.C.
nCE
You can leave the nCEO pin
DATA[]
unconnected or use it as a user
nCONFIG I/O pin when it does not feed
another device's nCE pin.
DCLK
and latch the
DCLK
or the internal oscillator. If you use
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CV-52007
2014.01.10