Altera Cyclone V Device Handbook page 473

cv_54001
2013.12.30
Slave Identifier
QSPIREGS
FPGAMGRREGS
ACPIDMAP
GPIO0
GPIO1
GPIO2
L3REGS
NANDDATA
QSPIDATA
USB0
USB1
NANDREGS
FPGAMGRDATA
CAN0
CAN1
UART0
UART1
I2C0
I2C1
I2C2
I2C3
SPTIMER0
SPTIMER1
SDRREGS
OSC1TIMER0
Introduction to Cyclone V Hard Processor System (HPS)
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Slave Title
Quad SPI flash controller
registers
FPGA manager registers
ACP ID mapper registers
GPIO0
GPIO1
GPIO2
L3 interconnect GPV
NAND controller data
Quad SPI flash data
USB0 OTG controller
registers
USB1 OTG controller
registers
NAND controller registers
FPGA manager configura-
tion data
CAN0 controller registers
CAN1 controller registers
UART0
UART1
I2C0
I2C1
I2C2
I2C3
SP Timer0
SP Timer1
SDRAM controller
subsystem registers
OSC1 Timer0
HPS Peripheral Region Address Map
Base Address
0xFF705000
0xFF706000
0xFF707000
0xFF708000
0xFF709000
0xFF70A000
0xFF800000
0xFF900000
0xFFA00000
0xFFB00000
0xFFB40000
0xFFB80000
0xFFB90000
0xFFC00000
0xFFC01000
0xFFC02000
0xFFC03000
0xFFC04000
0xFFC05000
0xFFC06000
0xFFC07000
0xFFC08000
0xFFC09000
0xFFC20000
0xFFD00000
1-17
Size
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
1 MB
1 MB
1 MB
256 KB
256 KB
64 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
4 KB
128 KB
4 KB
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