Pcie Supported Features - Altera Cyclone V Device Handbook

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PCIe Supported Features

Transceiver Channel Datapath
Figure 4-3: Transceiver Channel Datapath in a PIPE Configuration
Transmitter PMA
Receiver PMA
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Related Information
• Transceiver Architecture in Cyclone V Devices
• Cyclone V Device Datasheet
PCIe Supported Features
The PIPE configuration for the 2.5 Gbps (Gen1) and 5 Gbps (Gen2) data rates supports these features:
• PCIe-compliant synchronization state machine
• x1 and x4 link configurations
• ±300 parts per million (ppm)—total 600 ppm—clock rate compensation
• 8-bit FPGA fabric transceiver interface
• 16-bit FPGA fabric transceiver interface
• Transmitter buffer electrical idle
• Receiver detection
• 8B/10B encoder disparity control when transmitting compliance pattern
• Power state management (Electrical Idle only)
• Receiver status encoding
Altera Corporation
Transmitter PCS
Receiver PCS
Parallel and serial clocks
(only from the central clock divider)
Parallel and serial clocks (from the ×6 clock lines)
/2
/2
Central/ Local Clock Divider
Clock Divider
Transceiver Protocol Configurations in Cyclone V Devices
CMU PLL
Serial clock
(from the ×1 clock lines)
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CV-53004
2013.10.17
PCIe hard IP