Altera Cyclone V Device Handbook page 958

cv_54020
2013.12.30
receiver must respond with the acknowledge signal (ACK). When a slave-receiver does not respond with
an ACK pulse, the master aborts the transfer by issuing a STOP condition. The slave must leave the SDA
line high so that the master can abort the transfer. †
If the master-transmitter is transmitting data as shown in the following figure, then the slave-receiver responds
to the master-transmitter with an ACK pulse after every byte of data is received. †
Figure 20-6: Master-Transmitter Protocol †
Master-Receiver and Slave-Transmitter
If the master is receiving data as shown in the following figure, then the master responds to the slave-
transmitter with an ACK pulse after a byte of data has been received, except for the last byte. This is the way
the master-receiver notifies the slave-transmitter that this is the last byte. The slave-transmitter relinquishes
the SDA line after detecting the No Acknowledge (NACK) bit so that the master can issue a STOP condition.
†
When a master does not want to relinquish the bus with a STOP condition, the master can issue a RESTART
condition. This is identical to a START condition except it occurs after the ACK pulse. Operating in master
mode, the I
For a description of the combined format transactions that the I
Formats" section of this chapter. †
Note: The I
the target slave address register, IC_TAR can be reprogrammed. †
Figure 20-7: Master-Receiver Protocol †
I2C Controller
Send Feedback
7-Bit Address
S Slave Address
10-Bit Address
Slave Address
S
First 7 Bits
11110xxx
S: Start Condition
P: Stop Condition
R/W: Read/Write Pulse
A: Acknowledge (SDA Low)
A: No Acknowledge (SDA High)
2
C controller can then communicate with the same slave using a transfer of a different direction.
2
C controller must be inactive on the serial port (I2C_DYNAMIC_TAR_UPDATE = 1) before
7-Bit Address
S Slave Address
R/W
1 (Read)
10-Bit Address
Slave Address
S R/W
First 7 bits
11110xxx 0 (Write)
S: Start Condition
R: Restart Condition
P: Stop Condition
R/W: Read/Write Pulse
A: Acknowledge (SDA Low)
A: No Acknowledge (SDA High)
R/W A Data A
0 (Write)
Slave Address
R/W A
Second Byte
0 (Write)
From Master to Slave
From Slave to Master
A Data A Data P
A
Slave Address Slave Address
R
A A
Second Byte First 7 bits
11110xxx
From Master to Slave
From Slave to Master
Master-Receiver and Slave-Transmitter
Data P
A/A
A/A
A Data P
2
C controller supports, refer to "Combined
R/W A Data A
1 (Read)
20-7
P
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