Uart Controller; Uart Controller Features - Altera Cyclone V Device Handbook

2013.12.30
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The hard processor system (HPS) provides two UART controllers for asynchronous serial communication.
The UART controllers are based on an industry standard 16550 UART controller. The UART controllers
are instances of the Synopsys
(DW_apb_uart) peripheral.
Note: Portions
are registered trademarks of Synopsys, Inc. All documentation is provided "as is" and without any
warranty. Synopsys expressly disclaims any and all warranties, express, implied, or otherwise, including
the implied warranties of merchantability, fitness for a particular purpose, and non-infringement,
and any warranties arising out of a course of dealing or usage of trade.
†Paragraphs marked with the dagger (†) symbol are Synopsys Proprietary. Used with permission.

UART Controller Features

The UART controller provides the following functionality and features:
• Programmable character properties, such as number of data bits per character, optional parity bits, and
number of stop bits †
• Line break generation and detection †
• Direct memory access (DMA) controller interface
• Prioritized interrupt identification †
• Programmable baud rate
• False start bit detection †
• Automatic flow control mode per 16750 standard †
• Internal loopback mode support
• 128-bit transmit and receive FIFO buffer depth
• FIFO buffer status registers †
• FIFO buffer access mode (for FIFO buffer testing) enables write of receive FIFO buffer by master and
read of transmit FIFO buffer by master †
• Shadow registers reduce software overhead and provide programmable reset †
• Transmitter holding register empty (THRE) interrupt mode †
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UART Controller

®
APB Universal Asynchronous Receiver/Transmitter
21
ISO
9001:2008
Registered