Altera Cyclone V Device Handbook page 927

19-4
Serial Bit-Rate Clocks
Related Information
• Motorola SPI Protocol
• Texas Instruments Synchronous Serial Protocol (SSP)
• National Semiconductor Microwire Protocol
Serial Bit-Rate Clocks
SPI Master Bit-Rate Clock
The maximum frequency of the SPI master bit-rate clock (sclk_out) is one-half the frequency of SPI
master clock (spi_m_clk). This allows the shift control logic to capture data on one clock edge of
sclk_out and propagate data on the opposite edge. The sclk_out line toggles only when an active
transfer is in progress. At all other times it is held in an inactive state, as defined by the serial protocol under
which it operates. †
Figure 19-3: Maximum sclk_out/spi_m_clk Ratio
spi_m_clk
sclk_out
txd/rxd
The frequency of sclk_out can be derived from the equation below , where <SPI clock> is spi_m_clk
for the master SPI modules and l4_main_clk for the slave SPI modules. †
Fsclk_out = F<SPI clock> / SCKDV
SCKDV is a bit field in the register BAUDR, holding any even value in the range 2 to 65,534. If SCKDV is 0,
then sclk_out is disabled. †
The following equation describes the frequency ratio restrictions between the bit-rate clock sclk_out and
the SPI master peripheral clock. The SPI master peripheral clock must be at least double the offchip master
clock. †
Table 19-1: SPI Master Peripheral Clock
•
Fspi_m_clk >= 2 x (maximum Fsclk_out) †
SPI Slave Bit-Rate Clock
The minimum frequency of l4_main_clk depends on the operation of the slave peripheral. If the slave
device is receive only, the minimum frequency of l4_main_clk is six times the maximum expected
frequency of the bit-rate clock from the master device (sclk_in). The sclk_in signal is double
Altera Corporation
on page 19-12
Capture Drive 1 Capture 1
MSB
SPI Master Peripheral Clock
on page 19-13
on page 19-14
Drive 2 Capture 2 Drive 3
cv_54019
2013.12.30
Capture 3
SPI Controller
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