Msel Pin Settings - Altera Cyclone V Device Handbook

7-2

MSEL Pin Settings

Table 7-1: Configuration Modes and Features Supported by Cyclone V Devices
Mode
AS through the
EPCS and EPCQ
serial configura-
tion device
PS through CPLD
or external
microcontroller
FPP
CvP (PCIe)
JTAG
Instead of using an external flash or ROM, you can configure the Cyclone V devices through PCIe using
CvP. The CvP mode offers the fastest configuration rate and flexibility with the easy-to-use PCIe hard IP
block interface. The Cyclone V CvP implementation conforms to the PCIe 100 ms power-up-to-active time
requirement.
Related Information
Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide
Provides more information about the CvP configuration scheme.
MSEL Pin Settings
To select a configuration scheme, hardwire the
resistors.
Note: Do not drive the
(15)
Partial reconfiguration is an advanced feature of the device family. If you are interested in using partial
reconfiguration, contact Altera for support.
Altera Corporation
Data Max Clock Max Data
Width Rate Rate
(MHz) (Mbps)
1 bit, 4 100
bits
1 bit 125 125
8 bits 125
16 bits 125
x1, x2, —
and x4
lanes
1 bit 33
pins with a microprocessor or another device.
MSEL
Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices
Decompres- Design
sion Security
— Yes
Yes
— Yes
— Yes
— Yes
33 —
pins to V
MSEL
CCPGM
Partial Remote System
Reconfigura-
(15)
tion
Yes —
Yes —
Yes —
Parallel flash loader
Yes Yes
Yes Yes
— —
or GND without pull-up or pull-down
CV-52007
2014.01.10
Update
Yes
—
—
—
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