Resetting The Transceiver With The Phy Ip Embedded Reset Controller During Device Operation - Altera Cyclone V Device Handbook

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Resetting the Transceiver with the PHY IP Embedded Reset Controller during Device Operation

3. After the receiver calibration and reset sequence are complete, the rx_ready status signal is asserted
and remains asserted to indicate that the receiver is ready to receive data.
Note: If the tx_ready and rx_ready signals do not stay asserted, the reset sequence
did not complete successfully and the link will be down.
Figure 3-2: Reset Sequence Timing Diagram Using Embedded Reset Controller during Device
Power-Up
Resetting the Transceiver with the PHY IP Embedded Reset Controller during Device
Operation
Follow this reset sequence to reset the entire transceiver at any point during the device operation, to
re-establishing a link, or after certain dynamic reconfigurations.
The numbers in the following figure correspond to the numbered list, which guides you through the
transceiver reset sequence during device operation.
1. Assert phy_mgmt_clk_reset for two phy_mgmt_clk clock cycles to re-start the entire transceiver
reset sequence.
2. After the transmitter reset sequence is complete, the tx_ready status signal is asserted and remains
asserted to indicate that the transmitter is ready to transmit data.
3. After the receiver reset sequence is complete, the rx_ready status signal is asserted and remains asserted
to indicate that the receiver is ready to receive data.
Note: If the tx_ready and rx_ready signals do not stay asserted, the reset sequence
did not complete successfully and the link will be down.
Altera Corporation
Control Signals
mgmt_rst_reset 1
1
phy_mgmt_clk_reset
tx_ready
rx_ready
Status Signals
reconfig_busy
pll_locked
rx_is_lockedtodata
2
3
Transceiver Reset Control in Cyclone V Devices
CV-53003
2013.05.06
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