Uart Controller Programming Model; Dma Controller Operation - Altera Cyclone V Device Handbook

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2013.12.30
Figure 21-5: Interrupt Generation without Programmable THRE Interrupt Mode

UART Controller Programming Model

DMA Controller Operation

The UART controller includes a DMA controller interface to indicate when the receive FIFO buffer data is
available or when the transmit FIFO buffer requires data. The DMA requires two channels, one for transmit
and one for receive. The UART controller supports both single and burst transfers.
The FIFO buffer depth (FIFO_DEPTH) for both the RX and TX buffers in the UART controller is 128
entries.
Related Information
DMA Controller
For more information, refer to this DMA Controller chapter.
Transmit FIFO Underflow
During UART serial transfers, transmit FIFO requests are made to the DMA controller whenever the number
of entries in the transmit FIFO is less than or equal to the decoded level of the Transmit Empty Trigger
(TET) field in the FIFO Control Register (IIR_FCR), also known as the watermark level. The DMA controller
responds by writing a burst of data to the transmit FIFO buffer, of length specified as DMA burst length. †
UART Controller
Send Feedback
(INTR Is Asserted If
There Are No Interrupts)
on page 16-1
UART Controller Programming Model
Clear INTR
no
TX FIFO
Empty?
yes
THRE
no
Interrupt
Enabled?
yes
Set INTR
no
TX FIFO Not
Empty?
yes
21-7
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