Reset Effects; Altering Warm Reset System Response - Altera Cyclone V Device Handbook

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2013.12.30
The test reset (nTRST), test mode select (TMS), and test clock (TCK) pins are associated with the TAP reset
domain and are used to reset the TAP controller in the DAP. These pins are not connected to the reset
manager.
The nPOR and nRST pins are used to request cold and warm resets respectively. The nRST pin is an open
drain output as well. Any warm reset request causes the reset manager to drive the rst_pin_rst_n signal
output low, which drives the nRST pin low. The amount of time the reset manager pulls nRST low is
controlled by the nRST pin count field (nrstcnt) of the reset cycles count register (counts). This
technique can be used to reset external devices (such as external memories) connected to the HPS.

Reset Effects

The following list describes how reset affects HPS logic:
• The TAP reset domain ignores warm reset.
• The debug reset domain ignores warm reset.
• System reset domain cold resets ignore warm reset.
• Each module defines reset behavior individually.
Related Information
Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual
For more information, refer to the individual chapters in the Cyclone V Device Handbook, Volume 3.

Altering Warm Reset System Response

Registers in the clock manager, system manager, and reset manager control how warm reset affects the HPS.
You can control the impact of a warm reset on the clocks and I/O elements.
Altera strongly recommends using Altera-provided libraries to configure and control this functionality.
The default warm reset behavior takes all clocks and I/O elements through a cold reset response. As your
software becomes more stable or for debug purposes, you can alter the system response to a warm reset. The
following suggestions provide ways to alter the system response to a warm reset. None of the register bits
that control these items are affected by warm reset.
• Boot from on-chip RAM enables warm boot from on-chip RAM instead of the boot ROM. When
enabled, the boot ROM code validates the RAM code and jumps to it, making no changes to clocks or
any other system settings prior to executing user code from on-chip RAM.
• Disable safe mode on warm reset allows software to transition through a warm reset without affecting
the clocks. Because the boot ROM code indirectly configures the clock settings after warm reset, Altera
recommends to only disable safe mode when the HPS is not booting from a flash device.
• Disable safe mode on warm reset for the debug clocks keeps the debug clocks from being affected by
the assertion of safe mode request on a warm reset. This technique allows fast debug clocks, such as trace,
to continue running through a warm reset. When enabled, the clock manager puts the debug clocks to
their safe frequencies to respond to a safe mode request from the reset manager on a warm reset. Disable
safe mode on warm reset for the debug clocks only when you are running the debug clocks off the main
PLL VCO and you are certain the main PLL cannot be impacted by the event which caused the warm
reset.
• Use the osc1_clk clock for debug control keeps the debug base clock (main PLL C2 output) always
bypassed to the osc1_clk external clock, independent of other clock manager settings. When
implemented, disabling safe mode on warm reset for the debug clocks has no effect.
Reset Manager
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Reset Effects
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