Altera Cyclone V Device Handbook page 361

CV-53002
2013.05.06
Figure 2-18: Transmitter Datapath Interface Clocking for Three Bonded Channels
Selecting a Transmitter Datapath Interface Clock
Multiple non-bonded transmitter channels use a large portion of GCLK, RCLK, and PCLK resources.
Selecting a common clock driver for the transmitter datapath interface of all identical transmitter channels
saves clock resources.
Multiple transmitter channels that are non-bonded lead to high utilization of GCLK, RCLK, and PCLK
resources (one clock resource per channel). You can significantly reduce GCLK, RCLK, and PCLK resource
use for transmitter datapath clocks if the transmitter channels are identical.
Note: Identical transmitter channels have the same input reference clock source, transmit PLL configuration,
transmitter PMA, and PCS configuration, but may have different analog settings, such as transmitter
voltage output differential (V
To achieve the clock resource savings, select a common clock driver for the transmitter datapath interface
of all identical transmitter channels. The following figure shows six identical channels clocked by a single
clock (tx_clkout of channel 4).
Transceiver Clocking in Cyclone V Devices
Send Feedback
Channel 2
TX
Phase
Transmitter Data
Compensation
FIFO
Parallel Clock
Channel 1
TX
Phase
Transmitter Data
Compensation
FIFO
Parallel Clock
Channel 0
TX
Phase
Transmitter Data
Compensation
FIFO
Parallel Clock
), transmitter common-mode voltage (V
OD
Selecting a Transmitter Datapath Interface Clock
FPGA Fabric
Transmitter Data
tx_coreclkin[2]
Transmitter Data
tx_clkout[0]
Transmitter Data
Channel 2 Transmitter
Data and Control Logic
Channel 1 Transmitter
Data and Control Logic
tx_coreclkin[1]
Channel 0 Transmitter
Data and Control Logic
tx_coreclkin[0]
), or pre-emphasis settings.
CM
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