Altera Cyclone V Device Handbook page 969

20-18
Transmit FIFO Underflow
Related Information
DMA Controller
For details about the DMA burst length microcode setup, refer to the DMA controller chapter of the Cyclone
V Device Handbook, Volume 3.
Transmit FIFO Underflow
2
During I C serial transfers, transmit FIFO requests are made to the DMA controller whenever the number
of entries in the transmit FIFO is less than or equal to the value in DMA Transmit Data Level Register
(IC_DMA_TDLR), also known as the watermark level. The DMA controller responds by writing a burst of
data to the transmit FIFO buffer, of length specified as DMA burst length. †
Note: Data should be fetched from the DMA often enough for the transmit FIFO to perform serial transfers
continuously, that is, when the FIFO begins to empty, another DMA request should be triggered.
Otherwise, the FIFO will run out of the data (underflow) causing the maser to stall the transfer by
holding the SCL line low. To prevent this condition, you must set the watermark level correctly.†
Related Information
DMA Controller
For details about the DMA burst length microcode setup, refer to the DMA controller chapter of the Cyclone
V Device Handbook, Volume 3.
Transmit Watermark Level
Consider the example where the assumption is made: †
DMA burst length = FIFO_DEPTH - IC_DMA_TDLR †
Here the number of data items to be transferred in a DMA burst is equal to the empty space in the transmit
FIFO. Consider the following two different watermark level settings: †
• Case 1: IC_DMA_TDLR = 16: †
• Transmit FIFO watermark level = IC_DMA_TDLR = 16: †
• DMA burst length = FIFO_DEPTH - IC_DMA_TDLR = 48: †
2
• I C transmit FIFO_DEPTH = 64: †
• Block transaction size = 240: †
Figure 20-11: Transmit FIFO Watermark Level = 16
Altera Corporation
on page 16-1
on page 16-1
Transmit
FIFO Buffer
FIFO_DEPTH = 64
Transmit FIFO
Watermark Level
Data Out
FIFO_DEPTH - IC_DMA_TDLR = 48
Empty
Data In
IC_DMA_TDLR = 16
Full
DMA
Controller
I2C Controller
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2013.12.30