Jtag Configuration - Altera Cyclone V Device Handbook

7-24
Using PC Host and Download Cable
The pins of the devices in the chain are connected to GND, allowing configuration for these devices to
nCE
begin and end at the same time.
Using PC Host and Download Cable
To configure multiple Cyclone V devices, connect the devices to a download cable, as shown in the following
figure.
Figure 7-16: Multiple Device PS Configuration Using an Altera Download Cable
10 kΩ
You only need the pull-up resistors on
DATA0 and DCLK if the download cable
is the only configuration scheme used
on your board. This ensures that
DATA0 and DCLK are not left floating
after configuration. For example, if you
are also using a configuration device,
you do not need the pull-up resistors on
DATA0 and DCLK.
For more information, refer to
the MSEL pin settings.
When a device completes configuration, its
Configuration automatically begins for the second device.

JTAG Configuration

In Cyclone V devices, JTAG instructions take precedence over other configuration schemes.
The Quartus II software generates an SRAM Object File (.sof) that you can use for JTAG configuration using
a download cable in the Quartus II software programmer. Alternatively, you can use the JRunner software
with .rbf or a JAM
Code File (.jbc) with other third-party programmer tools.
Related Information
JTAG Boundary-Scan Testing in Cyclone V Devices
Provides more information about JTAG boundary-scan testing.
Device Configuration Pins
Provides more information about JTAG configuration pins.
Altera Corporation
FPGA Device 1
V
CCPGM
10 kΩ
MSEL[4..0]
V
CCPGM
nCE
GND
DATA0
nCONFIG
FPGA Device 2
MSEL[4..0]
nCE
DATA0
nCONFIG
™
Standard Test and Programming Language (STAPL) Format File (.jam) or JAM Byte
on page 7-6
Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices
V
CCPGM
V
CCPGM
10 kΩ
10 kΩ
CONF_DONE 10 kΩ (2)
nSTATUS
DCLK
nCEO
CONF_DONE
nSTATUS
DCLK
nCEO N.C.
pin is released low to activate the
nCEO
on page 9-1
Connect the pull-up resistor to the
same supply voltage (V CCIO ) as the
USB-Blaster, ByteBlaster II,
EthernetBlaster, or EthernetBlaster II
Download Cable
cable.
10-Pin Male Header
V
CCPGM
(PS Mode)
Pin 1
V
CCPGM
GND
V
IO
In the USB-Blaster and
ByteBlaster II cables, this
pin is connected to nCE
when you use it for AS
GND
programming. Otherwise,
this pin is a no connect.
pin of the next device.
nCE
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CV-52007
2014.01.10