Altera Cyclone V Device Handbook page 653

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2013.12.30
Command-Data Pair 4
31:28
Command 0x0
Data 0x0
Using Multitransaction DMA Commands
If you want the NAND flash controller DMA to perform cacheable accesses then you must configure the
cache bits by writing the l3master register in the nandgrp group in the system manager. The NAND
flash controller DMA must be idle before you use the system manager to change its cache capabilities.
You can issue non-DMA MAP10 commands while the NAND flash controller is in DMA mode. For example,
you might trigger a host-initiated page move between DMA commands, to achieve wear leveling. However,
do not interleave non-DMA MAP10 commands between the command-data pairs in a set of multitransaction
DMA commands. You must issue all four command-data pairs shown in the above tables before sending a
different command.
Do not issue MAP00, MAP01 or MAP11 commands while DMA is enabled.
MAP10 commands in multitransaction format are written to the Data register at offset 0x10 in nanddata,
the same as MAP10 commands in increment four (INCR4) format (described in Burst DMA Command).
Related Information
• Indexed Addressing
• Burst DMA Command
• System Manager
Burst DMA Command
You can initiate a DMA transfer by sending a command to the NAND flash controller as a burst transaction
of four 16-bit accesses. This form of DMA command might be useful for initiating DMA transfers from
custom IP in the FPGA fabric. Most processor cores cannot use this form of DMA command, because they
cannot control the width of the burst.
When DMA is enabled, the NAND flash controller recognizes the MAP10 pipeline DMA command, in the
format shown in the following table, as an INCR4 command. The address decoding for MAP10 pipeline
DMA command remains the same, as shown in MAP10 Address Mapping. The following table lists the
MAP10 burst DMA command structure; the burst DMA command carries the same information as the
multitransaction DMA command-data pairs, but in a very different format.
(24)
INT specifies the host interrupt to be generated at the end of the complete DMA transfer. INT controls the
value of the dma_cmd_comp bit of the intr_status0 register in the status group at the end of the
DMA transfer. INT can take on one of the following values:
0 Do not interrupt host. The dma_cmd_comp bit is set to 0.
1 Interrupt host. The dma_cmd_comp bit is set to 1.
NAND Flash Controller
Send Feedback
27:26 25:24 23:17
0x2 0x0 0x0
31:16
on page 10-5
on page 10-15
on page 14-1
Command-Data Pair 4
16 15:8
INT Burst length
(24)
15:12 11:8
0x2 0x4
10-15
7:0
0x0
7:0
0x0
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