Debugging Modules - Altera Cyclone V Device Handbook

cv_54006
2013.12.30

Debugging Modules

The MPU subsystem includes debugging resources through ARM CoreSight on-chip debugging and trace.
The following functionality is included:
• Individual program trace for each processor
• Event trace for the Cortex-A9 MPCore
• Cross triggering between processors and other HPS debugging features
Program Trace
Each processor has an independent PTM that provides real-time instruction flow trace. The PTM is compatible
with a number of third-party debugging tools.
The PTM provides trace data in a highly compressed format. The trace data includes tags for specific points
in the program execution flow, called waypoints. Waypoints are specific events or changes in the program
flow.
The PTM recognizes and tags the waypoints listed in
Table 6-10: Waypoints Supported by the PTM
Indirect branches
Direct branches
Instruction barrier instructions
Exceptions
Changes in processor instruction set state
Changes in processor security state
Context ID changes
Entry to and return from debug state when Halting
debug mode is enabled
The PTM optionally provides additional information for waypoints, including the following.
• Processor cycle count between waypoints
• Global timestamp values
For information about global timestamps, refer to the CoreSight Debug and Trace chapter in the Cyclone
V Device Handbook, Volume 3.
• Target addresses for direct branches
For more information about the PTM, refer to the CoreSight PTM-A9 Technical Reference Manual, available
on the ARM website (infocenter.arm.com).
Cortex-A9 Microprocessor Unit Subsystem
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Type
Table 6-10.
Additional Waypoint Information
Target address and condition code
Condition code
Location where the exception occurred
6-33
Debugging Modules
Altera Corporation