Embedded Memory Clocking Modes; Clocking Modes For Each Memory Mode - Altera Cyclone V Device Handbook

CV-52002
2013.05.06
Memory Mode
ROM
FIFO
Related Information
Internal Memory (RAM and ROM) User Guide
Provides more information memory modes.
RAM-Based Shift Register (ALTSHIFT_TAPS) Megafunction User Guide
Provides more information about implementing the shift register mode.
SCFIFO and DCFIFO Megafunctions User Guide
Provides more information about implementing FIFO buffers.

Embedded Memory Clocking Modes

This section describes the clocking modes for the Cyclone V memory blocks.
Caution:

Clocking Modes for Each Memory Mode

Table 2-10: Memory Blocks Clocking Modes Supported for Each Memory Mode
Clocking Mode
Single clock mode
Read/write clock mode
Embedded Memory Blocks in Cyclone V Devices
Send Feedback
M10K MLAB
Support Support
Yes Yes
Yes Yes
To avoid corrupting the memory contents, do not violate the setup or hold time on any of the
memory block input registers during read or write operations.
Single-Port
Yes
—
You can use the memory blocks as ROM.
Initialize the ROM contents of the memory blocks using a .mif
or .hex.
The address lines of the ROM are registered on M10K blocks
but can be unregistered on MLABs.
The outputs can be registered or unregistered.
The output registers can be asynchronously cleared.
The ROM read operation is identical to the read operation in
the single-port RAM configuration.
You can use the memory blocks as FIFO buffers. Use the SCFIFO
and DCFIFO megafunctions to implement single- and dual-clock
asynchronous FIFO buffers in your design.
For designs with many small and shallow FIFO buffers, the
MLABs are ideal for the FIFO mode. However, the MLABs do
not support mixed-width FIFO mode.
Memory Mode
Simple Dual- True Dual-
Port Port
Yes Yes
Yes —
Embedded Memory Clocking Modes
Description
ROM
Yes
—
2-11
FIFO
Yes
Yes
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