Altera Cyclone V Device Handbook page 391

CV-53004
2013.10.17
Figure 4-7: 9 Transceiver Channels and 2 PCIe HIP Blocks with PCIe x2 and x4 Channel Placement
The grayed out PCIe Hard IP block is not used in this example
Figure 4-8: 9 Transceiver Channels and 2 PCIe HIP Blocks with PCIe x1 Channel Placement
Transceiver Protocol Configurations in Cyclone V Devices
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PCIe Supported Configurations and Placement Guidelines
Transceiver Bank
Ch2
Ch1
Ch0
Transceiver Bank
Ch5
Ch4
Ch3
Ch2
PCIe x4
Ch1
PCIe x2
Ch0
Transceiver Bank
Ch2
Ch1
CMU PLL
PCIe x1
Ch0 Master
Transceiver Bank
Ch5
Ch4
Ch3
Ch2
Ch1
CMU PLL
PCIe x1
Ch0
Master
PCIe
Hard IP
CMU PLL
PCIe
Hard IP
Master
PCIe
Hard IP
PCIe
Hard IP
4-9
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