Altera Cyclone V Device Handbook page 732

11-54
CE-ATA CCS
Bits
cmd_index
wait_prvdata_complete
check_response_crc
Table 11-29: blksiz Register Settings for ATA Payload Transfer
Bits
31:16
15:0 (block_size)
Table 11-30: bytcnt Register Settings for ATA Payload Transfer
Bits
31:0
CE-ATA CCS
This section describes disabling the CCS, recovery after CCS timeout, and recovery after I/O read transmission
delay (N ) timeout.
ACIO
Disabling the CCS
While waiting for the CCS for an outstanding RW_BLK command, the host can disable the CCS by sending
a CCSD command:
• Send a CCSD command the controller sends the CCSD command to the CE-ATA card device if the
send_ccsd bit is set to 1 in the ctrl register of the controller. This bit can be set only after a response
is received for the RW_BLK command.
• Send an internal stop command send an internally-generated SD/SDIO STOP_TRANSMISSION
(CMD12) command after sending the CCSD pattern. If the send_auto_stop_ccsd bit of the ctrl
register is also set to 1 when the controller is set to send the CCSD pattern, the controller sends the
internally-generated STOP command to the CMD pin. After sending the STOP command, the controller
sets the acd bit in the rintsts register to 1.
Altera Corporation
Value
Command index
1
1
0
512, 1024 or 4096
<n>*block_size
†
†
†
Set this parameter to the command number. For
example, set to 24 for SD/SDIO WRITE_BLOCK
(CMD24) or 25 for WRITE_MULTIPLE_BLOCK
(CMD25).
• 0 for send command immediately
• 1 for send command after previous DTO
interrupt
• 0 for not checking response CRC
• 1 for checking response CRC
†
Value
Reserved bits set to 0
MMC block size can be 512, 1024
or 4096 bytes as negotiated by host
Value
Byte count must be an integer
multiple of the block size. For
ATA media access commands,
byte count must be a multiple of
4 KB.
(<n>*block_size = <x>*4 KB,
where <n> and <x> are integers)
†
Comment
Comment
Comment
SD/MMC Controller
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cv_54011
2013.12.30