Altera Cyclone V Device Handbook page 76

CV-52004
2014.01.10
Figure 4-19: PLL Locations for Cyclone V E A7 Device, Cyclone V GX C7 Device, and Cyclone V GT D7 Device
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
Clock Networks and PLLs in Cyclone V Devices
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CLK[8..11][p,n]
4
FRACTIONALPLL_X0_Y74
PLL Strip
4
FRACTIONALPLL_X0_Y56
2
FRACTIONALPLL_X0_Y32
2
4
FRACTIONALPLL_X0_Y15
4
FRACTIONALPLL_X0_Y1
CLK[0..3][p,n]
PLL Locations in Cyclone V Devices
Pins
CLK[10,11]
4 Logical Clocks
FRACTIONALPLL_X89_Y74
FRACTIONALPLL_X89_Y1
4
Logical Clocks
CLK[2,3]
Pins
2 Logical Clocks
4 2
Pins
Logical
CLK[4..5][p,n]
Clocks
4
2
Pins
Logical
CLK[6..7][p,n]
Clocks
2 Logical
Clocks
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4-19