Custom Configuration Channel Options - Altera Cyclone V Device Handbook

5-2

Custom Configuration Channel Options

Figure 5-2: Complete Datapath in a Custom Configuration
Based on your application requirements, you can enable, modify, or disable the blocks, except the deskew
FIFO block, as shown in the following figure.
Serial
Clock
Parallel Clock
Custom Configuration Channel Options
There are multiple channel options when you use Custom Configuration.
The supported interface width varies depending on the usage of the byte serializer/deserializer (SERDES),
and the 8B/10B encoder or decoder. The byte serializer or deserializer is assumed to be enabled. Otherwise,
the maximum data rate supported is half of the specified value.
The maximum supported data rate varies depending on the customization.
Table 5-1: Maximum Supported Data Rate
The following table shows the maximum supported data rate for the fastest speed grade in Standard PCS (transceiver
speed grade 6) for Cyclone V GX and SX devices, and (transceiver speed grade 5) for Cyclone V GT and ST devices.
Data Configuration
Single-width
Altera Corporation
Transmitter PMA Transmitter PCS
Receiver PMA Receiver PCS
PCS-FPGA Fabric Interface Width
PMA-PCS
Interface
8B/10B
Width
Enabled
8 —
8
10
16
/2
/2
Serial Clock
Parallel Clock
Maximum Data
Rate for GX
8B/10B
and SX (Mbps)
Disabled
8 1,500
16 3,000
10 1,875
20 3,125
Transceiver Custom Configurations in Cyclone V Devices
2013.05.06
FPGA Fabric
tx_parallel data
tx_coreclkin
tx_clkout
rx_parallel data
rx_coreclkin
rx_clkout
The serial and parallel clocks are
sourced from the clock divider.
Maximum Data Rate for GT
and ST (Mbps)
1,500
3,000
1,875
3,750
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