Device Operation - Altera Cyclone V Device Handbook

18-14

Device Operation

Device Operation
Device Initialization
The following process sets up the USB OTG controller as a USB device:
1. After power up, the USB OTG controller must be set to the desired device speed by writing to the Device
Speed (devspd) bits in the Device Configuration Register (dcfg) in the Device Mode Registers (devgrp)
group. After the device speed is set, the controller waits for a USB host to detect the USB port as a device
port.
2. When an external host detects the USB port, the host performs a port reset, which generates an interrupt
to the USB device software. The USB Reset (usbrst) bit in the Interrupt (port reset) register in
the Global Registers (globgrp) group is set. The device software then sets up the data FIFO buffer to
receive a SETUP packet from the external host. Endpoint 0 is not enabled yet.
3. After completion of the port reset, the operation speed required by the external host is known. Software
reads the device speed status and sets up all the remaining required transaction fields to enable control
endpoint 0.
After completion of this process, the device is receiving SOF packets, and is ready for the USB host to set up
the device's control endpoint.
Device Transaction
When configured as a device, the USB OTG controller uses a single FIFO buffer to receive the data for all
the OUT endpoints. The receive FIFO buffer holds the status of the received data packet, including the byte
count, the data packet ID (PID), and the validity of the received data. The DMA controller reads the data
out of the FIFO buffer as the data are received. If a FIFO buffer overflow condition occurs, the controller
responds to the OUT packet with a NAK, and internally rewinds the pointers.
For IN endpoints, the controller uses dedicated transmit buffers for each endpoint. The application does
not need to predict the order in which the USB host will access the nonperiodic endpoints. If a FIFO buffer
underrun condition occurs during transmit, the controller inverts the cyclic redundancy code (CRC) to
mark the packet as corrupt on the USB link.
The application handles one data packet at a time per endpoint in transaction-level operations. The software
receives an interrupt on completion of every packet. Based on the handshake response received on the USB
link, the application determines whether to retry the transaction or proceed with the next transaction, until
all packets in the transfer are completed.
IN Transactions
For an IN transaction, the application performs the following steps:
1. Enables the endpoint
2. Triggers the DMA engine to write the associated data packet to the corresponding transmit FIFO buffer
3. Waits for the packet completion interrupt from the controller
When an IN token is received on an endpoint when the associated transmit FIFO buffer does not contain
sufficient data, the controller performs the following steps:
1. Generates an interrupt
2. Returns a NAK handshake to the USB host
Altera Corporation
cv_54018
2013.12.30
USB 2.0 OTG Controller
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