Altera Cyclone V Device Handbook page 883

17-34
Receive Descriptor Acquisition
Receive Descriptor Acquisition
The receive Engine always attempts to acquire an extra descriptor in anticipation of an incoming frame.
Descriptor acquisition is attempted if any of the following conditions is satisfied: †
• Bit 1 (Start or Stop Receive) of Register 6 (Operation Mode Register) has been set immediately after being
placed in the Run state. †
• The data buffer of current descriptor is full before the frame ends for the current transfer. †
• The controller has completed frame reception, but the current receive descriptor is not yet closed. †
• The receive process has been suspended because of a host-owned buffer (RDES0[31] = 0) and a new
frame is received. †
• A Receive poll demand has been issued. †
Receive Frame Processing
The MAC transfers the received frames to the Host memory only when the frame passes the address filter
and frame size is greater than or equal to configurable threshold bytes set for the receive FIFO buffer of
MTL, or when the complete frame is written to the FIFO buffer in Store-and-Forward mode. †
If the frame fails the address filtering, it is dropped in the MAC block itself (unless Bit 31 (Receive All) of
Register 1 (MAC Frame Filter) is set). Frames that are shorter than 64 bytes, because of collision or premature
termination, can be removed from the MTL receive FIFO buffer. †
After 64 (configurable threshold) bytes have been received, the MTL block requests the DMA block to begin
transferring the frame data to the receive Buffer pointed by the current descriptor. The DMA sets First
Descriptor (RDES0[9]) after the DMA Host interface becomes ready to receive a data transfer (if DMA is
not fetching transmit data from the host), to delimit the frame. The descriptors are released when the Own
(RDES[31]) bit is reset to 0, either as the Data buffer fills up or as the last segment of the frame is transferred
to the receive buffer. If the frame is contained in a single descriptor, both Last Descriptor (RDES[8]) and
First Descriptor (RDES[9]) are set.
The DMA fetches the next descriptor, sets the Last Descriptor (RDES[8]) bit, and releases the RDES0 status
bits in the previous frame descriptor. Then the DMA sets the Bit 6 (Receive Interrupt) of Register 5 (Status
Register). The same process repeats unless the DMA encounters a descriptor flagged as being owned by the
host. If this occurs, the receive Process sets the Bit 7 (Receive Buffer Unavailable) of Register 5 (Status
Register) and then enters the Suspend state. The position in the receive list is retained. †
Receive Process Suspended
If a new receive frame arrives while the receive Process is in Suspend state, the DMA refetches the current
descriptor in the Host memory. If the descriptor is now owned by the DMA, the receive Process re-enters
the Run state and starts frame reception. If the descriptor is still owned by the host, by default, the DMA
discards the current frame at the top of the MTL RX FIFO buffer and increments the missed frame counter.
If more than one frame is stored in the MTL EX FIFO buffer, the process repeats. †
The discarding or flushing of the frame at the top of the MTL EX FIFO buffer can be avoided by disabling
Flushing (Bit 24 of Register 6 (Operation Mode Register)). In such conditions, the receive process sets the
Receive Buffer Unavailable status and returns to the Suspend state. †
Interrupts
Interrupts can be generated as a result of various events. The DMA Register 5 (Status Register) contains all
the bits that might cause an interrupt. Register 7 (Interrupt Enable Register) contains an enable bit for each
of the events that can cause an interrupt.
There are two groups of interrupts, Normal and Abnormal, as described in Register 5 (Status Register).
Interrupts are cleared by writing a 1 to the corresponding bit position. When all the enabled interrupts within
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2013.12.30