Pcie Supported Configurations And Placement Guidelines - Altera Cyclone V Device Handbook

CV-53004
2013.10.17
Note: The PCIe reverse parallel loopback is the only loopback option that is supported in PIPE configura-
tions.
Figure 4-4: PIPE Reverse Parallel Loopback Mode Datapath
Transmitter PMA
Receiver PMA
Parallel Clock
Serial Clock
Parallel and Serial Clocks

PCIe Supported Configurations and Placement Guidelines

Placement by the Quartus II software may vary with design and device. The following figures show examples
of transceiver channel and PCIe Hard IP block locations, supported x1, x2, and x4 bonding configurations,
and channel placement guidelines. The Quartus II software automatically places the CMU PLL in a channel
different from that of the data channels.
Note: This section shows the supported PCIe channel placement if you use both the top
and bottom PCIe Hard IP blocks in the device separately.
In the following figures, channels shaded in blue provide the high-speed serial clock. Channels
shaded in gray are data channels.
Transceiver Protocol Configurations in Cyclone V Devices
Send Feedback
Transmitter PCS
Reverse Parallel
Loopback Path
Receiver PCS
Parallel and serial clocks
(only from the central clock divider)
Parallel and serial clocks (from the ×6 clock lines)
PCIe Supported Configurations and Placement Guidelines
/2
/2
Central/ Local Clock Divider
Clock Divider
CMU PLL
Serial clock
(from the ×1 clock lines)
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PCIe hard IP