Pma Architecture - Altera Cyclone V Device Handbook

CV-53001
2013.05.06

PMA Architecture

The PMA includes the transmitter and receiver datapaths, clock multiplier unit (CMU) PLL—configured
from the channel PLL—and the clock divider. The analog circuitry and differential on-chip termination
(OCT) in the PMA requires the calibration block to compensate for process, voltage, and temperature
variations (PVT).
Each transmitter channel has a clock divider. There are two types of clock dividers, depending on the channel
location in a transceiver bank:
• Channels 0, 2, 3, and 5—local clock divider
• Channels 1 and 4—central clock divider
Using clocks from the clock lines and CMU PLL, the clock divider generates the parallel and serial clock
sources for transmitter and optionally for the receiver PCS. The central clock divider can additionally feed
the clock lines used to bond channels compared to the local clock divider.
Figure 1-8: PMA Block Diagram of a Transceiver Channel in Cyclone V Devices
Related Information
• Altera Transceiver PHY IP Core User Guide
• IP Compiler for PCI Express User Guide
Transceiver Architecture in Cyclone V Devices
Send Feedback
From the Transmitter PCS
or FPGA Fabric (1)
High-speed
Clock
Networks
To the Receiver PCS
or FPGA Fabric (1)
Notes:
1. The channel PLL provides the serial clock when configured as a CMU PLL.
2. The channel PLL recovers the clock and serial data stream when configured as a CDR.
Transmitter PMA
Serializer
Transmitter
Clock
Divider
(2)
Channel PLL
Deserializer
(CMU PLL or
CDR)
Receiver PMA
PMA Architecture
Buffer
Physical
Transmission
Medium
Receiver
Buffer
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