Altera Cyclone V Device Handbook page 776

13-6
Power Up Phase
Power Up Phase
In this phase, the VCC is ramping up and has yet to reach normal levels. This phase completes when the on-
chip voltage detector determines that the VCC has reached normal levels.
Reset Phase
The FPGA manager resets the FPGA portion of the SoC device when the FPGA configuration signal
(nCONFIG) is driven low. The HPS configures the FPGA by writing a 1 to the nconfigpull bit of the
ctrl register. This action causes the FPGA portion of the device to reset and perform the following actions:
1. Clear the FPGA configuration RAM bits
2. Tri-state all FPGA user I/O pins
3. Pull the nSTATUS and CONF_DONE pins low
4. Use the FPGA CB to read the values of the MSEL pins to determine the configuration scheme
The nconfigpull bit of the ctrl register needs to be set to 0 when the FPGA has successfully entered
the reset phase. Setting the bit releases the FPGA from the reset phase and transitions to the configuration
phase.
Note: You must set the cdratio and cfgwdth bits of the ctrl register appropriately before the FPGA
enters the reset phase.
Configuration Phase
To configure the FPGA using the HPS, software sets the axicfgen bit of the ctrl register to 1. Software
then sends configuration data to the FPGA by writing data to the write data register (data) in the FPGA
manager module configuration data address map. Software polls the CONF_DONE pin by reading the
gpio_instatus register to determine if the FPGA configuration is successful. When configuration is
successful, software sets the axicfgen bit of the ctrl register to 0. The FPGA user I/O pins are still tri-
stated in this phase.
After successfully completing the configuration phase, the FPGA transitions to the initialization phase. To
delay configuring the FPGA, set the confdonepull bit of the ctrl register to 1.
Related Information
• Booting and Configuration
For more information about configuring the FPGA through the HPS, refer to the Booting and Configuration
appendix in the Cyclone V Device Handbook, Volume 3.
• Booting and Configuration Introduction
For more information about configuring the FPGA through the HPS, refer to the Booting and Configuration
appendix.
Initialization Phase
In this phase, the FPGA prepares to enter user mode. The internal oscillator in the FPGA portion of the
device is the default clock source for the initialization phase. Alternatively, the configuration image can
specify the CLKUSR or the DCLK pins as the clock source. The alternate clock source controls when the
FPGA enters user mode.
Altera Corporation
on page 30-1
cv_54013
2013.12.30
FPGA Manager
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