Altera Cyclone V Device Handbook page 565

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cv_54006
2013.12.30
GIC
Source Block
Interrupt
Number
(6)
180
NAND
181
NAND
182
NAND
183
QSPI
184
QSPI
185
QSPI
186
SPI0
187
SPI1
188
SPI2
189
SPI3
190
I2C0
191
I2C1
192
I2C2
193
I2C3
194
UART0
195
UART1
196
GPIO0
197
GPIO1
198
GPIO2
(6)
To ensure that you are using the correct GIC interrupt number, your code should refer to the symbolic interrupt
name, as shown in the Interrupt Name column. Symbolic interrupt names are defined in a header file distributed
with the source installation for your operating system.
(11)
This interrupt combines the following interrupts: ssi_txe_intr, ssi_txo_intr, ssi_rxf_intr,
ssi_rxo_intr, ssi_rxu_intr, and ssi_mst_intr.
(12)
This interrupt combines the following interrupts: ic_rx_under_intr, ic_rx_full_intr, ic_tx_
over_intr, ic_tx_empty_intr, ic_rd_req_intr, ic_tx_abrt_intr, ic_rx_done_intr,
ic_activity_intr, ic_stop_det_intr, ic_start_det_intr, and ic_gen_call_intr.
Cortex-A9 Microprocessor Unit Subsystem
Send Feedback
Interrupt Name
nandw_ecc_uncorrected_IRQ
nande_ecc_corrected_IRQ
nande_ecc_uncorrected_IRQ
qspi_IRQ
qspi_ecc_corrected_IRQ
qspi_ecc_uncorrected_IRQ
spi0_IRQ
spi1_IRQ
spi2_IRQ
spi3_IRQ
i2c0_IRQ
i2c1_IRQ
i2c2_IRQ
i2c3_IRQ
uart0_IRQ
uart1_IRQ
gpio0_IRQ
gpio1_IRQ
gpio2_IRQ
GIC Interrupt Map for the Cyclone V SoC HPS
Combined
Interrupts
(11)
(11)
(11)
(11)
(12)
(12)
(12)
(12)
6-19
Triggering
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
Level
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