Altera Cyclone V Device Handbook page 485

cv_54002
2013.12.30
Figure 2-4: Peripheral Clock Group Divide and Gating
Clock Manager
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emac0_base_clk
Peripheral
C0
PLL
emac1_base_clk
C1
periph_qspi_base_clk
C2
periph_nand_sdmmc_base_clk
C3
periph_base_clk
C4
h2f_user1_base_clk
C5
Peripheral Clock Group
Clock Gate
Clock Gate
To Flash Controller Clocks
To Flash Controller Clocks
Divide by
Clock Gate
1, 2, 4, 8, or 16
Divide by
Clock Gate
1, 2, 4, 8, or 16
Divide by
Clock Gate
1, 2, 4, 8, or 16
Divide by
Clock Gate
1, 2, 4, 8, or 16
24-Bit
Clock Gate
Divider
Clock Gate
2-11
emac0_clk
emac1_clk
To main PLL group
l4_mp_clk & l4_sp_clk
multiplexer
usb_mp_clk
spi_m_clk
can0_clk
can1_clk
gpio_db_clk
h2f_user1_clock
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