Altera Cyclone V Device Handbook page 194

6-20
DLL Phase-Shift
DLL
DLL_BR
DLL Phase-Shift
The DLL can shift the incoming DQS signals by 0° or 90°. The shifted DQS signal is then used as the clock
for the DQ IOE input registers, depending on the number of DQS delay chains used.
All DQS pins referenced to the same DLL, can have their input signal phase shifted by a different degree
amount but all must be referenced at one particular frequency. However, not all phase-shift combinations
are supported. The phase shifts on the DQS pins referenced by the same DLL must all be a multiple of 90°.
The 7-bit DQS delay settings from the DLL vary with PVT to implement the phase-shift delay. For example,
with a 0° shift, the DQS signal bypasses both the DLL and DQS logic blocks. The Quartus II software
automatically sets the DQ input delay chains, so that the skew between the DQ and DQS pins at the DQ IOE
registers is negligible if a 0° shift is implemented. You can feed the DQS delay settings to the DQS logic block
and logic array.
The shifted DQS signal goes to the DQS bus to clock the IOE input registers of the DQ pins. The signal can
also go into the logic array for resynchronization if you are not using IOE read FIFO for resynchronization.
For Cyclone V SoC devices, you can feed the hard processor system (HPS) DQS delay settings to the HPS
DQS logic block only.
Figure 6-7: Simplified Diagram of the DQS Phase-Shift Circuitry
This figure shows a simple block diagram of the DLL. All features of the DQS phase-shift circuitry are
accessible from the UniPHY megafunction in the Quartus II software.
Input Reference
This clock can
come from a PLL
output clock or an
input clock pin
The input reference clock goes into the DLL to a chain of up to eight delay elements. The phase comparator
compares the signal coming out of the end of the delay chain block to the input reference clock. The phase
comparator then issues the
7-bit delay setting (DQS delay settings) that increases or decreases the delay through the delay element chain
to bring the input reference clock and the signals coming out of the delay element chain in phase.
The DLL can be reset from either the logic array or a user I/O pin. Each time the DLL is reset, you must wait
for 2,560 clock cycles for the DLL to lock before you can capture the data properly. The DLL phase comparator
requires 2,560 clock cycles to lock and calculate the correct input clock period.
For the frequency range of each DLL frequency mode, refer to the device datasheet.
Altera Corporation
Top Left
—
aload
clk
Clock
Phase
Comparator
signal to the Gray-code counter. This signal increments or decrements a
upndn
PLL
Top Right Bottom Left
—
upndnin
Up/Down
Counter
upndninclkena
7
delayctrlout [6:0]
Delay Chains
7 dqsupdate
External Memory Interfaces in Cyclone V Devices
Bottom Right
—
pllout
DLL
DQS delay settings
can go to the logic
array and DQS logic
block
DQS Delay
Settings
7
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CV-52006
2014.01.10