Altera Cyclone V Device Handbook page 536

cv_54005
2013.12.30
Related Information
Cortex-A9 Microprocessor Unit Subsystem
For more information about the ECC option of the L2 cache or about interconnect master IDs, refer to the
Cortex-A9 Microprocessor Unit Subsystem chapter.
FPGA-to-HPS Bridge Slave Signals
The FPGA-to-HPS bridge slave address channels support user-sideband signals, routed to the ACP in the
MPU subsystem. All the signals have a fixed width except the data and write strobes for the read and write
data channels. The variable width signals depend on the data width setting of the bridge. The following tables
list all the signals exposed by the FPGA-to-HPS slave interface to the FPGA fabric.
Table 5-4: FPGA-to-HPS Bridge Slave Write Address Channel Signals
Signal
AWID
AWADDR
AWLEN
AWSIZE
AWBURST
AWLOCK
AWCACHE
AWPROT
AWVALID
AWREADY
AWUSER
Table 5-5: FPGA-to-HPS Bridge Slave Write Data Channel Signals
Signal
WID
WDATA
WSTRB
WLAST
WVALID
WREADY
HPS-FPGA AXI Bridges
Send Feedback
Width Direction
8 bits Input
32 bits Input
4 bits Input
3 bits Input
2 bits Input
2 bits Input
4 bits Input
3 bits Input
1 bit Input
1 bit Output
5 bits Input
Width Direction
8 bits Input
32, 64, or 128 bits Input
4, 8, or 16 bits Input
1 bit Input
1 bit Input
1 bit Output
FPGA-to-HPS Bridge Slave Signals
on page 6-1
Write address ID
Write address
Burst length
Burst size
Burst type
Lock type Valid values are 00 (normal access) and
01 (exclusive access)
Cache policy type
Protection type
Write address channel valid
Write address channel ready
User sideband signals
Write ID
Write data
Write data strobes
Write last data identifier
Write data channel valid
Write data channel ready
Description
Description
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