Altera Cyclone V Device Handbook page 944

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• Write CTRLR0 to set transfer parameters. If the transfer is sequential and the SPI master receives
data, write CTRLR1 with the number of frames in the transfer minus 1. For example, if you want to
receive four data frames, write this register with 3.
• Write BAUDR to set the baud rate for the transfer.
• Write TXFTLR and RXFTLR to set FIFO buffer threshold levels.
• Write the IMR register to set up interrupt masks.
You can write the SER register to enable the target slave for selection. If a slave is enabled here, the transfer
begins as soon as one valid data entry is present in the transmit FIFO buffer. If no slaves are enabled prior
to writing to the DR register, the transfer does not begin until a slave is enabled.
3. Enable the SPI master by writing 1 to the SSIENR register.
4. If the SPI master transmits data, write the control and data words into the transmit FIFO buffer (write
DR). If the SPI master receives data, write the control word or words into the transmit FIFO buffer. If no
slaves were enabled in the SER register at this point, enable now to begin the transfer.
5. Poll the BUSY status to wait for the transfer to complete. If a transmit FIFO empty interrupt request is
made, write the transmit FIFO buffer (write DR). If a receive FIFO full interrupt request is made, read
the receive FIFO buffer (read DR).
SPI Controller
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Master Microwire Serial Transfers
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