Altera Cyclone V Device Handbook page 960

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2013.12.30
Figure 20-9: Multiple Master Arbitration †
The bus control is determined by address or master code and data sent by competing masters, so there is no
central master nor any order of priority on the bus. †
Arbitration is not allowed between the following conditions: †
• A RESTART condition and a data bit †
• A STOP condition and a data bit †
• A RESTART condition and a STOP condition †
Slaves are not involved in the arbitration process. †
Clock Synchronization
When two or more masters try to transfer information on the bus at the same time, they must arbitrate and
synchronize the SCL clock. All masters generate their own clock to transfer messages. Data is valid only
during the high period of SCL clock. Clock synchronization is performed using the wired-AND connection
to the SCL signal. When the master transitions the SCL clock to 0, the master starts counting the low time
of the SCL clock and transitions the SCL clock signal to 1 at the beginning of the next clock period. However,
if another master is holding the SCL line to 0, then the master goes into a HIGH wait state until the SCL
clock line transitions to 1. †
All masters then count off their high time, and the master with the shortest high time transitions the SCL
line to 0. The masters then counts out their low time and the one with the longest low time forces the other
master into a HIGH wait state. Therefore, a synchronized SCL clock is generated, which is illustrated in the
following figure. Optionally, slaves may hold the SCL line low to slow down the timing on the I
I2C Controller
Send Feedback
MSB
DATA1
DATA2
SDA
SCL
SDA Lines Up with
DATA1 Start Condition
1
Matching Data
MSB
MSB
Clock Synchronization
DATA1 Loses Arbitration
0
SDA Mirrors DATA2
20-9
2
C bus. †
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