6.144 Gbps Cpri Support Capability In Gt Devices; Transceiver Channel Architecture - Altera Cyclone V Device Handbook

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6.144 Gbps CPRI Support Capability in GT Devices

The transmitter and receiver in a channel are structured into PMA and PCS sections:
• PMA—converts serial data to parallel data and vice versa for connecting the FPGA to a serial transmission
medium.
• PCS—prepares the parallel data for transmission across a physical medium or restores the data to its
original form using hard digital logic implementation.
6.144 Gbps CPRI Support Capability in GT Devices
You can configure Cyclone V GT devices to support 6.144 Gbps for CPRI protocol only. The Cyclone V GT
device supports up to three full duplex channels that are compliant to the 6.144 Gbps CPRI protocol for
every two transceiver banks. The transceivers are grouped in transceiver banks of three channels.
Altera recommends that you increase the VCCE_GXBL and VCCL_GXBL to a nominal value of 1.2 V in
order to be compliant to the 6.144Gbps CPRI protocol. The reference clock frequency for the 6.144 Gbps
CPRI channel must be ≥ 307.2 MHz.
Related Information
Transceiver Protocol Configurations in Cyclone V Devices

Transceiver Channel Architecture

Cyclone V transceiver channels support the following interface methods with the FPGA fabric:
• Directly—bypassing the PIPE interface for the PCIe interface and PCIe hard IP block
• Through the PIPE interface and PCIe hard IP block—for hard IP implementation of the PCIe protocol
stacks (PHY/MAC, data link layer, and transaction layer)
Figure 1-7: Transceiver Channel Block Diagram in Cyclone V Devices
Note:
1. Only certain transceiver channels support interfacing to the PCIe hard IP block.
You can bond multiple channels to implement a multilane link.
Related Information
Transceiver Banks
Altera Corporation
Transceiver Channel
Transmitter PMA
Receiver PMA
on page 1-3
Transmitter PCS
Receiver PCS
Transceiver Architecture in Cyclone V Devices
CV-53001
2013.05.06
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