Altera Cyclone V Device Handbook page 703

cv_54011
2013.12.30
Table 11-13: Non-Data Transfer Commands and Requirements
Cmd_index
Response_
expect
Response_
length
Check_
response_crc
Data_expected
Read/write
Transfer_mode
Send_auto_stop
Wait_prevdata_
complete
Stop_abort_
cmd
Clock Control Block
The clock control block provides different clock frequencies required for SD/MMC/CE-ATA cards. The
clock control block has one clock divider, which is used to generate different card clock frequencies.
The clock frequency of a card depends on the following clock ctrl register settings:
(33)
Num_bytes = Number of bytes specified as per the lock card data structure. Refer to the SD specification and
the MMC specification.
SD/MMC Controller
Send Feedback
PROGRAM_ SEND_WRITE_
CSD (CMD27) PROT (CMD30)
cmd Register Setup
0x1B=27 0x1E=30
1 1
0 0
1 1
1 1
1 0
0 0
0 0
0 0
0 0
cmdarg Register Setup
Stuff bits 32-bit write
protect data
address
blksiz Register Setup
16 4
bytcnt Register Setup
16 4
†
†
LOCK_ SD_ SEND_NUM_
UNLOCK STATUS WR_BLOCKS
(CMD42) (ACMD13) (ACMD22)
0x2A=42 0x0D=13 0x16=22
1 1 1
0 0 0
1 1 1
1 1 1
1 0 0
0 0 0
0 0 0
0 0 0
0 0 0
Stuff bits Stuff Stuff bits
bits
Num_ 64 4
†
(33)
bytes
Num_ 64 4
†
(33)
bytes
11-25
Clock Control Block
SEND_SCR
(ACMD51)
0x33=51
1
0
1
1
0
0
0
0
0
Stuff
bits
8
8
†
†
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