Interconnect Address Map And Register Definitions; Document Revision History - Altera Cyclone V Device Handbook

4-20

Interconnect Address Map and Register Definitions

Related Information
• Reset Manager
• Cortex-A9 Microprocessor Unit Subsystem
Contains information about virtual ID mapping by the ACP ID mapper.
Interconnect Address Map and Register Definitions
The address map and register definitions reside in the hps.html file that accompanies this handbook volume.
Click the link to open the file.
To view the module description and base address, scroll to and click the link for the following module
instance:
• l3regs
To then view the register and field descriptions, scroll to and click the register names. The register addresses
are offsets relative to the base address of each module instance.
Related Information
• Introduction to Cyclone V Hard Processor System (HPS)
The base addresses of all modules are also listed in the Introduction to the Hard Processor chapter.
• Cyclone V SoC HPS Address Map and Register Definitions

Document Revision History

Table 4-6: Document Revision History
Date
December 2013
November 2012
June 2012
January 2012
Altera Corporation
on page 3-1
2013.12.30
1.2
1.1
1.0
on page 6-1
on page 1-1
Version
Maintenance release
Minor updates.
• Added main switch
• Rearranged functional
• Simplified address remapping
• Added address map and
Initial release.
Changes
connectivity matrix table.
description sections.
section.
register definitions section.
Interconnect
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2013.12.30