Altera Cyclone V Device Handbook page 214

6-40
Document Revision History
Date
May 2013
December 2012
Altera Corporation
Version
2013.05.06 Moved all links to the Related Information section of respective topics
for easy reference.
Added link to the known document issues in the Knowledge Base.
Added the supported minimum operating frequencies for the supported
memory interface standards.
Added packages and updated the DQ/DQS groups of Cyclone V E, GX,
GT, and SX devices.
Added the number of MPFE command, write-data, and read-data ports
for each Cyclone V E, GX, and GT device.
Added a note about the usable hard memory controller pin assignments
for the F484 package of the Cyclone V E A9, GX C9, and GT D9 devices.
Updated the M386 package to M383.
Removed the F672 package from the Cyclone V E A5 device in the table
listing Cyclone V E hard memory controller widths.
Added the U484 package for the Cyclone V GX C9 device in the table
listing Cyclone V GX hard memory controller widths.
Updated the hard memory controller widths of Cyclone V E, GX, SX,
and ST.
Removed the restrictions on using the bottom hard memory controller
of the Cyclone V GX C5 device if the configuration is 3.3/3.0 V.
Added note to clarify that the DQS phase-shift circuitry figures show
all possible connections and the device pin-out files have per package
information.
2012.11.28 Reorganized content and updated template.
Added a list of supported external memory interface standards using
the hard memory controller and soft memory controller.
Added performance information for external memory interfaces and
the HPS external memory interfaces.
Separated the DQ/DQS groups tables into separate topics for each device
variant for easy reference.
Updated the DQ/DQS numbers and device packages for the Cyclone V
E, GX, GT, SX, and ST variants.
Moved the PHYCLK networks pin placement guideline to the
Pin and FPGA Resources
Handbook.
Moved information from the "Design Considerations" section into
relevant topics.
Removed the "DDR2 SDRAM Interface" and "DDR3 SDRAM DIMM"
sections. Refer to the relevant sections in the
Handbook
Added the I/O and DQS configuration blocks topic.
Updated the term "Multiport logic" to "multi-port front end" (MPFE).
Added information about the hard memory controller interface widths
for the Cyclone V E, GX, GT, SX, and ST variants.
Changes
chapter of the External Memory Interface
for the information.
External Memory Interfaces in Cyclone V Devices
Planning
External Memory Interface
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2014.01.10