Altera Cyclone V Device Handbook page 879

Hide thumbs Also See for Cyclone V:
Table of Contents

Advertisement

17-30
Transmit Frame Processing
Figure 17-8: TX DMA Operation in OSF Mode
Transmit Frame Processing
The transmit DMA expects that the data buffers contain complete Ethernet frames, excluding preamble,
pad bytes, and FCS fields. The DA, SA, and Type/Len fields contain valid data. If the transmit descriptor
indicates that the MAC must disable CRC or PAD insertion, the buffer must have complete Ethernet frames
(excluding preamble), including the CRC bytes. †
Frames can be data-chained and can span several buffers. Frames must be delimited by the First Descriptor
(TDES1[29]) and the Last Descriptor (TDES1[30]), respectively. †
Altera Corporation
Poll Demand
Tx DMA
Suspended
Previous Frame
Status Available
no
Timestamp
Present?
yes
Write Timestamp to RDES2 &
TDES3 for Previous Frame
yes
Error?
no
Close Intermediate
Write Status Word to
Descriptor
Previous Frame's TDES0
no
Error?
yes
Start
Start
Tx DMA
Stop
Rx DMA
(Re-)Fetch Next
Descriptor
yes
Error?
no
no
Own Bit Set?
yes
Transfer Data
from Buffer(s)
yes
Error?
no
no
Frame
no
yes
Second
Transfer
Frame?
Complete?
yes
Wait for Previous
Frame's TX Status
Write Timestamp
yes
Timestamp
to TDES2 & TDES3
Present?
for Previous Frame
no
no
Write Status Word to
Error?
Previous Frame's TDES0
no
Error?
yes
Ethernet Media Access Controller
Send Feedback
cv_54017
2013.12.30

Advertisement

Table of Contents
loading

Table of Contents