Functional Description Of The Gpio Interface; Debounce Operation - Altera Cyclone V Device Handbook

22-2

Functional Description of the GPIO Interface

Figure 22-1: Cyclone V SoC GPIO
Table 22-1: GPIO Interface pin table
Pin Mux Name
GPIO [28:0]
GPIO [57:29]
GPIO [66:58]
HLGPI [13:0]
Functional Description of the GPIO Interface

Debounce Operation

The GPIO modules provided in the HPS include optional debounce capabilities. The external signal can be
debounced to remove any spurious glitches that are less than one period of the external debouncing clock,
gpio_db_clk. †
When input interrupt signals are debounced using the gpio_db_clk debounce clock, the signals must
be active for a minimum of two cycles of the debounce clock to guarantee that they are registered. Any input
pulse widths less than a debounce clock period are filtered out. If the input signal pulse width is between
one and two debounce clock widths it may or may not be filtered out, depending on its phase relationship
to the debounce clock. If the input pulse spans two rising edges of the debounce clock, it is registered. If it
spans only one rising edge, it is not registered. †
The figure below shows a timing diagram of the debounce circuitry for both cases: a bounced input signal,
and later, a propagated input signal..
Altera Corporation
gpio_rst_n[n]
Reset
Manager
clk
Clock
Manager
GPIO[28:0]
GPIO 0
I/O
GPIO[57:29]
GPIO 1
GPIO[66:58]
GPIO 2
HLGPI[13:0]
L4 Peripheral Bus
Mapped to signal name
GPIO 0 [28:0]
GPIO 1 [28:0]
GPIO 2 [8:0]
GPIO 2 [26:13]
GPIO Interface
gpio_intr_in
Interrupt &
Control
Register
Block
Slave
Interface
Comments
Input / Output
Input / Output
Input / Output
Input only
Cortex A9 Subsystem
Core Generic Interrupt
Controller
General-Purpose I/O Interface
Send Feedback
cv_54022
2013.12.30