Altera Cyclone V Device Handbook page 685

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The SD/MMC controller provides outputs to notify the system manager when single-bit correctable errors
are detected (and corrected), and when double-bit (uncorrectable) errors are detected. The system manager
generates an interrupt to the GIC when an ECC error is detected.
Related Information
System Manager
Internal DMA Controller
The internal DMA controller has a CSR and a single transmit or receive engine, which transfers data from
system memory to the card and vice versa. The controller uses a descriptor mechanism to efficiently move
data from source to destination with minimal host processor intervention. You can set up the controller to
interrupt the host processor in situations such as transmit and receive data transfer completion from the
card, as well as other normal or error conditions. The DMA controller and the host driver communicate
through a single data structure.
The internal DMA controller transfers the data received from the card to the data buffer in the system
memory, and transfers transmit data from the data buffer in the memory to the controller's FIFO buffer.
Descriptors that reside in the system memory act as pointers to these buffers.
A data buffer resides in the physical memory space of the system memory and consists of complete or partial
data. The buffer status is maintained in the descriptor. Data chaining refers to data that spans multiple data
buffers. However, a single descriptor cannot span multiple data buffers.
A single descriptor is used for both reception and transmission. The base address of the list is written into
the descriptor list base address register (dbaddr). A descriptor list is forward linked. The last descriptor
can point back to the first entry to create a ring structure. The descriptor list resides in the physical memory
address space of the host. Each descriptor can point to a maximum of two data buffers.
Internal DMA Controller Descriptors
The internal DMA controller uses these types of descriptor structures:
• Dual-buffer structure The distance between two descriptors is determined by the skip length value
written to the descriptor skip length field (dsl) of the bus mode register (bmod).
• Chain structure Each descriptor points to a unique buffer, and to the next descriptor in a linked list.
Figure 11-4: Dual-Buffer Descriptor Structure
SD/MMC Controller
Send Feedback
on page 14-1
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The Distance Between 2
Descriptors Is Determined
by the DSL Value Programmed
in the BMOD Register
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Descriptor A
Descriptor B
Descriptor C
Internal DMA Controller
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Data Buffer 1
Data Buffer 2
Data Buffer 1
Data Buffer 2
Data Buffer 1
Data Buffer 2
Altera Corporation
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