Altera Cyclone V Device Handbook page 325

1-38
Word Aligner in Bit-Slip Mode
PCS Mode
Double Width
Word Aligner in Bit-Slip Mode
In bit-slip mode, the word aligner is controlled by the rx_bitslip bit of the pcs8g_rx_wa_control
register. At every 0-1 transition of the rx_bitslip bit of the pcs8g_rx_wa_control register, the
bit-slip circuitry slips one bit into the received data stream, effectively shifting the word boundary by one
bit. Also in bit-slip mode, the word aligner pcs8g_rx_wa_status register bit for rx_patterndetect
is driven high for one parallel clock cycle when the received data after bit-slipping matches the 16-bit word
alignment pattern programmed.
To achieve word alignment, you can implement a bit-slip controller in the FPGA fabric that monitors the
rx_parallel_data signal, the rx_patterndetect signal, or both, and controls them with the
rx_bitslip signal.
Table 1-19: Word Aligner in Bit-Slip Mode
PCS Mode
Single Width
Double Width
Note: For every bit slipped in the word aligner, the earliest bit received is lost.
Altera Corporation
PMA PCS
Interface Width
(bits)
16 1. After the rx_digitalreset signal deasserts, regardless of the
setting in the rx_enapatternalign register, the word aligner
20
synchronizes to the first predefined alignment pattern found.
2. Any alignment pattern found thereafter in a different word
boundary does not cause the word aligner to resynchronize to this
new word boundary.
3. To resynchronize to the new word boundary, create a 0-to-1
transition in the rx_enapatternalign register.
4. When the word aligner synchronized to the new word boundary,
the rx_patterndetect and rx_syncstatus signals will
assert for one parallel clock cycle. The rx_syncstatus signal
will deassert if the next rising edge of rx_enapatternalign
is detected.
PMA PCS Interface Width
(bits)
8
10
16
20
Word Alignment Operation
Word Alignment Operation
1. At every rising edge to the rx_bitslip signal, the word
aligner slips one bit into the received data.
2. When bit-slipping shifts a complete round of the data bus
width, the word boundary is back to the original boundary.
3. Use the rx_patterndetect signal assertion or check
the data output to indicate completion of alignment
process—where the word aligner output matches the
predefined alignment pattern.
Transceiver Architecture in Cyclone V Devices
CV-53001
2013.05.06
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