Dedicated Reference Clock Pins - Altera Cyclone V Device Handbook

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Dedicated Reference Clock Pins

Sources
Generic CLK pin
Core clock network (GCLK, RCLK,
PCLK)
Dedicated Reference Clock Pins
Cyclone V devices have one dedicated reference clock (refclk) pin for each bank of three transceiver
channels.
The dedicated reference clock pins drive the channel PLL in channel 1 or 4 directly. This option provides
the best quality of input reference clock to the transmitter PLL and CDR.
Note: For specifications about the input frequency supported by the refclk pins, refer to the Cyclone V
Device Datasheet.
As shown in the following figure the dedicated refclk pin direct connection to the channel PLL (which
can be configured either as a CMU PLL or CDR) is only available in channel 1 of a transceiver bank and
channel 4 of the neighboring transceiver bank.
(6)
The lower number indicates better jitter performance.
Altera Corporation
Transmitter PLL
CDR
CMU PLL
No
No
Jitter Performance
No
No
Transceiver Clocking in Cyclone V Devices
CV-53002
2013.05.06
(6)
5
6
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