Altera Cyclone V Device Handbook page 844

16-48
Unaligned Source Address to Aligned Destination Address
Figure 16-28: Aligned to Unaligned Program
The first DMALD instruction loads four doublewords but because the destination address is unaligned, the
DMAC shifts them by four bytes and therefore it uses five entries in the MFIFO buffer.
Each DMAST requires only four entries of data, and therefore the extra entry remains in use for the duration
of the program, until it is emptied by the last DMAST.
This example has a static requirement of one MFIFO buffer entry and a dynamic requirement of four MFIFO
buffer entries.
Unaligned Source Address to Aligned Destination Address
In this program, the source address is unaligned with the AXI data bus width but the destination address is
aligned. The source address is not aligned to the source burst size so the first DMALD instruction reads in
less data than the DMAST. Therefore, an extra DMALD is required to satisfy the first DMAST.
DMAMOV CCR, SB4 SS64 DB4 DS64
DMAMOV SAR, 0x1004
DMAMOV DAR, 0x4000
DMALD ; shown as a in the figure below
DMALP 15
DMALD ; shown as b1, ... b, bn in the figure below
DMAST ; shown as c in the figure below
DMALPEND
DMAMOV CCR, SB1 SS32 DB4 DS64
DMALD ; shown as d in the figure below
DMAST ; shown as e in the figure below
DMAEND
Altera Corporation
a a a a
n
1
5
1
b b b b
0
c
Data from
DMALD DMALD
7
a a a a
1 1 1 1
Data for
a a a a a a
1 1 1 1 1 1
first DMAST
a a a a a a
1 1 1 1 1 1
a a a a a a
1 1 1 1 1 1
a a a a a a
1 1
a a a a a a a a
a a a a a a a a
Data for a a a a a a a a
15x DMAST
Data for a a
n n
last DMAST
DMAST
0
a a
1 1
a a
1 1
a a
1 1
a a
1 1
a a
n n
DMA Controller
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2013.12.30