Altera Cyclone V Device Handbook page 603

cv_54008
2013.12.30
MPU Subsystem Interface
The SDRAM controller is connected to the MPU subsystem with a dedicated 64-bit AXI interface, operating
on the mpu_l2_ram_clk clock domain.
L3 Interconnect Interface
The SDRAM controller is connected to the L3 interconnect with a dedicated 32-bit AXI interface, operating
on the l3_main_clk clock domain.
CSR Interface
The CSR interface is connected the level 4 (L4) bus and operates on the l4_sp_clk clock domain. The
MPU subsystem uses the CSR interface to configure the controller and PHY, for example, setting the memory
timing parameter values or placing the memory to a low power state. The CSR interface also provides access
to the status registers in the controller and PHY.
FPGA-to-HPS SDRAM Interface
The FPGA-to-HPS SDRAM interface provides masters implemented in the FPGA fabric access to the SDRAM
controller subsystem in the HPS. The interface has three ports types that are used to construct the following
AXI or Avalon-MM interfaces:
• Command ports issue read and write commands, and for receive write acknowledge responses
• 64-bit read data ports receive data returned from a memory read
• 64-bit write data ports transmit write data
The FPGA-to-HPS SDRAM interface supports six command ports, allowing up to six Avalon-MM interfaces
or three AXI interfaces. Each command port can be used to implement either a read or write command port
for AXI, or be used as part of an Avalon-MM interface. The AXI and Avalon-MM interfaces can be configured
to support 32-, 64-, 128-, and 256-bit data.
The following table lists the FPGA-to-HPS SDRAM controller interface ports connected to the FPGA.
Table 8-1: FPGA-to-HPS SDRAM Controller Port Types
Command
64-bit read data
64-bit write data
The FPGA-to-HPS SDRAM controller interface can be configured with the following characteristics:
• Avalon-MM interfaces and AXI interfaces can be mixed and matched as required by the fabric logic,
within the bounds of the number of ports provided to the fabric.
• Each Avalon-MM or AXI interface of the FPGA-to-HPS SDRAM interface operates on an independent
clock domain.
• The FPGA-to-HPS SDRAM interfaces are configured during FPGA configuration.
The following table shows the number of ports needed to configure different bus protocols, based on type
and data width.
SDRAM Controller Subsystem
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Port Type
SDRAM Controller Subsystem Interfaces
Number
6
4
4
8-3
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