Altera Cyclone V Device Handbook page 697

cv_54011
2013.12.30
Note: After the N
commands, or the STOP command. The Data Read Timeout (DRTO) interrupt might be set to 1
while a STOP_TRANSMISSION command is transmitted out of the controller, in which case the
data read timeout boot data start bit (bds) and the dto bit in the rintsts register are set to 1.
Data Path
The data path block reads the data FIFO buffer and transmits data on the card bus during a write data
transfer, or receives data and writes it to the FIFO buffer during a read data transfer. The data path loads
new data parameters data expected, read/write data transfer, stream/block transfer, block size, byte count,
card type, timeout registers whenever a data transfer command is not in progress. If the data transfer
expected bit (data_expected) in the cmd register is set to 1, the new command is a data transfer command
and the data path starts one of the following actions:
• Transmits data if the read/write bit = 1
• Receives data if read/write bit = 0
Data Transmit
The data transmit state machine starts data transmission two clock cycles after a response for the data write
command is received. This occurs even if the command path detects a response error or response CRC error.
If a response is not received from the card because of a response timeout, data is not transmitted. Depending
upon the value of the transfer mode bit (transfer_mode) in the cmd register, the data transmit state
machine puts data on the card data bus in a stream or in blocks.
Figure 11-8: Data Transmit State Machine
Stream Data Transmit
If the transfer_mode bit in the cmd register is set to 1, the transfer is a stream-write data transfer. The
data path reads data from the FIFO buffer from the BIU and transmits in a stream to the card data bus. If
the FIFO buffer becomes empty, the card clock is stopped and restarted once data is available in the FIFO
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buffer.
If the bytcnt register is reset to 0, the transfer is an open-ended stream-write data transfer. During this
data transfer, the data path continuously transmits data in a stream until the host software issues an SD/SDIO
STOP command. A stream data transfer is terminated when the end bit of the STOP command and end bit
of the data match over two clock cycles.
SD/MMC Controller
Send Feedback
timeout, the application must abort the command by sending the CCSD and STOP
ACIO
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load_new_cmd,
data_expected, Write
Data & Block Transfer
Stop Data Command
Tx
Data Block
Byte Count
Remaining != 0
Data Not Busy
Block Done
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Stop Data Command
Data Tx
Idle
load_new_command,
data_expected, Write
Data & Stream Transfer
Data Stream
Byte Count
Remaining = 0
or Suspend/Stop
Data Command
Rx
CRC Status
Data Path
Tx
Altera Corporation
11-19
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